Recent Invited Presentations

1.      International Flexible Electronics Conference, Tarragona, Spain, April 2008
“Low Temperature Prepared a-Si:H Memory Devices for Flexible Substrates.” 

2.      International Reliability Physics Symposium (IRPS)  Nanoelectronic Device Reliability, 04/27-05/01/08, Phoenix, AZ
“Failure Process of the Nanocrystals Embedded High-k Film for Nonvolatile Memories.”

3.      MRS Symposium on  Amorphous and Polycrystalline Thin Film Silicon Science and Technology, San Francisco, CA, 03/24-28/08
“Discharge of Floating Gate a-Si:H TFT Nonvolatile Memories with Electrical, Optical, and Thermal Methods.”

4.      4th International TFT Conference – ITC ’08, Seoul, Korea, 01/24-25/08
“Charge and Discharge of Floating-Gate a-Si:H TFT Nonvolatile Memories.”

5.      MOEA, Kaoshung, Taiwan, 12/09/07
“Nonvolatile Memory Embedded a-Si:H TFTs.”

6.      Keynote speech, 14th International Workshop on Active Matrix Flat Panel Displays and Devices (AM-FPD 07), Hyogo, Japan, 07/11-13/07
“TFT Technology as a Competitor or Collaborator of IC.”  

7.      14th International Workshop on Active Matrix Flat Panel Displays and Devices (AM-FPD 07), Hyogo, Japan, 07/11-13/07
“Review of ECS TFT 8 Symposium on New Technology Developments.” 

8.      International Display Manufacturing Conference, SID Taipei, Taiwan 07/05/07
“TFTs Beyond LCD Pixel Driving and Experience for 450 mm ULSIC Process Development.”

9.      National Chiao Tung University, Display Institute, 07/06/07
“TFTs Beyond LCD Pixel Driving and Experience for 450 mm ULSIC Process Development.”

10.  Award seminar in 211th Electrochemical Society Meeting, Electronics and Photonics Division award, Chicago, IL 05/06-11/07
“Thin Film Transistor and ULSIC Technologies - Parallel or Crossing?” 

11.  University of Tennessee, Department of Chemical Engineering, Knoxville, TN, 11/30/06
“ Microelectronics Research – from Nano Science to Giga Engineering.”

12.  4th International Symp. on High Dielectric Constant Gate Stacks, Electrochemical Society, Cancun, Mexico 10/31-11/2/06
“Mixed Oxide High-k Gate Dielectrics - Interface Layer Structure, Breakdown Mechanism, and Memories.”

13.  University of Michigan, Department of Chemical Engineering, Ann Arbor, MI, 09/28/06
“From Nano to Giga Electronics Research - Our Approach.”

14.  2006 Lester Eastman Conf. High Performance Devices, Cornell University, Ithaca, NY 08/02-04/06
“High Performance High-k Gate Dielectrics Based on Mixed Oxides.”   

15.  Lester Eastman Conf. On High Performance Devices, Cornell University, Ithaca, NY 08/02-04/06 (co-authors T. Yuan, et al.)
“Charge Trapping and Dielectric Relaxation in Connection with Breakdown of High-k Gate Dielectric Stacks.”   

16.  Components and Enabling Technologies for High Image Quality Smart Panels, Ministry of Economic Affairs, HsinChu, Taiwan, 07/06
“TFT Applications beyond LCDs.”

17.  Active Matrix Flat Panel Displays (AMFPD) Conference, Tokyo, Japan, 07/5/06
“TFT Sensors and New Applications.”

18.  Hitachi Central Research Laboratory, Tokyo, Japan, 07/04/06
“Non-LCD TFT Applications.” 

19.  2nd International Symp. on Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing, Electrochem. Soc./IEEE, Denver, CO, 05/7-12/06
”Mixed Oxide High-k Gate Dielectrics.” 

20.  6th International Conference on Reactive Plasmas (ICRP-6), Sendai, Japan, 01/24/06-01/27/06
“Room Temperature Plasma Etching of Copper for ULSIC and TFTs.”

21.  Osaka University, Center for Atomic and Molecular Technologies, 01/23/06
“Plasma Thin Film Processes- fundamentals and applications”

22.  National Science Council and TSMC sponsored Seminar, National Tsing-Hua University, Chemical Engineering Dept., 12/14/05
“Thin Film Technology for Transistor Fabrication - from nano MOSFETs to Giga TFT Arrays.”

23.  National Science Council and TSMC sponsored Seminar, National Cheng Kung University, Materials Sci. and Eng. Dept., 12/16/05
“Thin Film Technology for Transistor Fabrication - from nano MOSFETs to Giga TFT Arrays.” 

24.  Jilin University, College of Electronics Science and Engineering, ChangChun, China, 10/10/05
“Amorphous Silicon TFTs – Fundamental and Applications.”

25.  Chinese Academy of Sciences, ChangChun Institute of Applied Chemistry, China, 10/11/05
“Nano and Giga Electronics Research.”

26.  Nankai University, Optoelectronics Institute, Tienjin, China, 10/15/05
“Amorphous Silicon TFTs – Fundamental and Applications.”

27.  US, China, and Japan Joint Chemical Engineering Conference ’05,
Keynote speech, Microelectronics Section, 10/05. 
“Multidisciplinary Nano and Microelectronics: current status and future development.” 

28.  University of Texas, Chemical Engineering Department, Austin, TX, 09/06/05 
“From Nano and Giga Electronics Research.” 

29.  Nara Institute of Science and Technology, Materials Science Department, Nara, Japan 06/07/05
“a-Si:H TFTs Fundamentals and New Applications.” 

30.  National Taiwan University, Chemical Engineering Department, Taipei, 05/02/05
“From Nano to Giga Electronics Research.”

31.  2005 Symposium on Nano Device Technology (SNDT), Keynote Speech, Hsin-chu, Taiwan, 05/04/05.
“Doping of High-k Dielectric Thin Films for Future Nano MOSFETs.”

32.  2005 Symposium on Nano Device Technology (SNDT), Short course tutorial lecture, 05/03/05.
“High-k gate dielectrics - urgent nano issues in ULSIC.” 

33.  University of Tennessee, Materials Science and Engineering Department, 04/05.
“Challenges in Sub 0.1 mm Era Materials Processing.”    

34.  International TFT Conference ’05, KyungHee University, Seoul, Korea, 03/14-15/05. 
“P- and n-channel a-Si:H TFTs.” 

35.  SEMATECH, Autsin, TX, 01/07/05.
“Doping of HfO2 Gate Dielectric.” 

36.  Darpa/MTO Macroelectronics Workshop, Phoenix, AZ, 11/17/04.
“Giga Electronics Multidisciplinary (GEM) Research Center - a TFT Initiative.”

37.  IEEE International Reliability Workshop Conference Tutorial Lecture
Stanford Sierra Camp, South Lake Tahoe, CA, 10/19/04.
“A Review on TFT Process and Device Reliability Issues.”   

38.  University of Limerick, Materials and Surface Science Institute and Department of Physics, Ireland, 06/30/04.
“Copper Etching with a New Plasma-based Process and Application to p-channel TFTs.”

39.  Waseda University, Department of Industry Chemistry, Tokyo, Japan, 06/22/04 
“A Novel Plasma-Based, Room-Temperature Copper Etch Process and Its Applications.”

40.  AUO, Hsin-chu, Taiwan, 06/17/04.
“A Novel Plasma-Based, Room-Temperature Copper Etch Process and Its Application to p-channel TFTs.” 

41.  2004 Taiwan Display Conference, Taipei, Taiwan, 06/10/04.
“p-channel a-Si:H TFT with copper electrodes defined with a new plasma-based etching method. ”

42.  Tuskegee University, Tuskegee, AL, 08/03/04.
“Giga Electronics Era – Technology Challenges.”

43.  National Science Council Distinguished Scholar Seminar
National Nano Device Laboratory, Hsin-chu, Taiwan, 12/24/03.
“Nano Challenges in Sub-0.1 Micrometer VLSI Era: high k, low k, Copper, and 157 nm Lithography.”  

44.  National Science Council Distinguished Scholar Seminar
National Synchrotron Radiation Research Center, Hsin-chu, Taiwan, 12/25/03.
“Some Nano Issues in Future IC Fabrication.”

45.  National Science Council Distinguished Scholar Seminar, National Taiwan University, Department of Chemistry, 12/26/03.
“Plasma Reactions in Nano and Microelectronics Fabrication.”

46.  ALTEDEC, Japan, 06/09/03.
“A New, Room-Temperature, High-Rate Plasma-Based Copper Etch Process.”

47.  Cambridge University, Engineering Department, 05/02/03.
“Challenges in Sub 0.1 mm Era -Packing More Devices and Functions into the Circuit.”

48.  ULSI Process Integration III Symposium, Electrochem. Soc. Meeting, Paris 04/29/03.
“Thin Film Transistors in ULSI –Status and Future.”

49.  National Nano Laboratory, Hsin-chu, Taiwan, 12/20/02.
“Sub 10 nm Doped Metal Oxides for Improved High k Dielectric Properties.”

50.  National Synchrotron Radiation Research Center, Hsin-chu, Taiwan, 12/20/02.
“Sub 10 nm Doped Metal Oxides for Improved High k Dielectric Properties.”

51.  Giga-to-Nano electronics Seminar, University of Waterloo, Waterloo, Canada, 09/27/02.
“Challenges in Sub-0.1 Micron VLSI Devices: Advanced High k and Low k Materials and Processes.”

52.  Silicon Technology Seminar, Texas Instruments, Dallas, TX, 05/24/02.
“Copper Fine Patterns Etched with a Plasma Based Processes.”

53.  Solid State Technology and Devices Seminar, University of California, Electrical Engineering Department, Berkeley, CA 09/07/01.
“A New Room-Temperature Plasma-Based Copper Etch Process.”

54.  Keynote Speech, 2001 CACS Meeting (Chinese American Chemical Society), Houston, TX 03/26/01.
“Semiconductor Technology - Challenges for Interdisciplinary Research & Production.”

55.  SemiconBay Internet Forum, Expert Viewpoint, 11:00 AM, 01/17/01.
“Higher Education for Semiconductor Process Engineer.”

56.  Lindsay Lecture, Texas A&M University, Chemical Engineering Department
College Station, TX 09/01/00.
“Challenges on Thin Film Materials and Processes for Sub-0.1 Micrometer ULSICs.”

57.  IBM Almaden Research Center, San Jose, CA, 06/26/00.
“A New Plasma-Based Copper Etching Process.”

58.  Samsung Electronics, TFT LCD Development Center, Kyungki-Do, Korea, 12/15/99.
“Trends on Thin Film Transistor Research.”

59.  Physics Department, Kyung Hee University, Seoul, Korea, 12/14/99.
“Material, Device, and Process Relationship in a-Si:H Thin Film Transistor.”

60.  International Semiconductor Device Research Symposium, Charlottesville, VA, 12/1-3/99.
“Material Issues in a-Si:H and Poly-Si Thin-film Transistors for Microelectronics and Optoelectronics Applications”

61.  Electrochem. Soc. South Texas Section, College Station, TX, 10/29/99.
“What is a thin film transistor?”

62.  NSF and DARPA Sensitive Skin Workshop, 10/14/00-10/15/00.
“Integrated Interlaced Sensor Arrays and Display.”

63.  SemiconBay Internet Forum, Expert Viewpoint, 11:00 AM, 05/31/00.
“Searching for High K Gate Dielectric Materials for Future Generation CMOS Transistors.”

64.  EC Summer School on Advanced Materials for Industrial Applications,
Aristotle University of Thessaloniki, Department of Physics, Kavala, Greece, 06/20/99.
“CFC-Free Plasma Technology in High-Tech Industry.”

65.  5th International Symp. On Sputtering and Plasma Processes, Japan Applied Physics Society, Kanazawa, Japan, 06/99.
“Some Issues on Hydrogen and Hydrogenation of Plasma Enhanced Chemical Vapor Deposited Films in a-Si:H Thin Film Transistors.”

66.  Dow Chemical Corp. Research Center, Midland, MI 02/01/99.
“Thin Film Materials for TFTs and VLSIC Devices.”

67.  Energy Research Institute, Kyoto University, Kyoto, Japan, 12/98.
“Plasma Etching and Deposition for TFTs.”

68.  Sanyo Microelectronics Research Center, Gifu, Japan 12/98.
“Process, Materials, and Devices Relationship in a-Si:H TFT.”

69.  IEEE International Conference on Plasma Science,
ICOPS 98, Flat Panel Displays, Raleigh, NC, 06/02/98.
“Plasma Thin Film Processes for TFT LCD Manufacturing.”

70.  Molecular Electronics and Photonics Symposium, European Materials Research Society, Strasbourg, France, 06/16/98.
“Interface Engineering in Thin Film Transistor.”

71.  Display Device Development Center, Matsushita Electric Ind. Co., Ltd., Osaka, Japan, 06/11/97.
“a-Si:H and Poly-Si Thin Film Transistors Structures and Materials.”

72.  4th International Symp. on Sputtering and Plasma Processes,
ISSP '97, Kanazawa, Japan, 06/04/97.
“PECVD Silicon Nitride as a Gate Dielectric Film for Amorphous Silicon Thin Film Transistors - a Critical Review.”

73.  Hitachi Research Laboratory, Hitachi Ltd., Ibaraki, Japan, 06/03/97.
“Thin Film Transistor Technology - a Global View.”

74.  Electrical and Computer Science and Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, 04/21/97.
“Thin Film Transistor Technologies.”

75.  54th Japan Domestic Meeting on Plasma Etching of Indium Tin Oxide,
Japan Technology Transfer Society, Kanazawa, Japan, 12/10/97.
“Fundamentals of Dry Etching of Indium Tin Oxide Thin Film.”

76.  TFT LCD Research Center, Lucky-Gold Star Electronics Inc., Anyang, Korea, 12/4/97.
“Review of Thin Film Transistor Technologies.”

77.  Physics Department, Kyung Hee University, Seoul, Korea, 12/3/97.
“Thin Film Transistor Technologies - a Global View.”

78.  Electronic Materials and Processing Research Laboratory, Pennsylvania State University, University Park, PA, 08/12/96.
“Thin Film Technologies in Thin Film Transistor Fabrication.”

79.  MKS Technology Roadmap Workshop, MKS, Inc., Andover, MA, 07/25/96.
“Flat Panel Display Roadmap.”

80.  Ministry of Education, Opto-Electronic Office, Taiwan, ROC and Society for Information Display, Taiwan Division, 10/95.
“Thin Film Transistor Process Engineering.”

81.  Electrical Engineering Department, Solid State Technology and Device Seminar,
University of California, Berkeley, CA, 04/95.
“A Global View of Thin Film Transistor Technologies.”

82.  Electrical Engineering Department, Stanford University, Palo Alto, CA, 04/95.
“A Global View of Thin Film Transistor Technologies.”

83.  Departments of Electrical Engineering, Materials Science, and Chemical Engineering,
National Taiwan University, Taipei, 12/19/94.
“Device Influence of Plasma Etching and Deposition Processes.”

84.  National Nano Laboratory, National Chiao-Tung University, Hsin-chu, 12/20/94.
“Device Influence of Plasma Etching and Deposition Processes.”

85.  Department of Chemical Engineering, National Cheng Kung University, Tainan, Taiwan, 12/21/94.
“Device Influence of Plasma Etching and Deposition Processes.”

86.  NATO Advanced Study Institute, Symposium Ion, Electron, and Laser Modification and Processing of Materials, Chalkidiki, Greece, 05/94.
“Deposition and Etching Mechanisms in Plasma Thin Film Processes.”

87.  International Semiconductor Device Research Symposium, University of Virginia, Charlottesville, VA, 12/01/93.
“Plasma Processes for Amorphous Silicon Thin Film Transistors.”

88.  National Nano Lab, National Chiao-Tung University, Hsin-chu, Taiwan, 06/93.
“Plasma Enhanced Chemical Vapor Deposition Thin Film Technology for Thin Film Transistors.”

89.  Materials and Electronics Lab, Xerox Webster Research Center, Rochester, NY, 10/92.
“Reactive Ion Etching Processes and Materials Characterization of Thin Film Transistor Materials.”

90.  Symp. Thin Film Transistor Technologies I, Electrochem. Soc. National Meeting, Toronto, Canada 10/92.
“Reactive Ion Etching of Thin Film Transistor Materials with Chlorofluorocarbon-Free Gases.”

91.  Symp. Lightning, Display, and Imaging Technology, Electrochem. Soc. National Meeting, Toronto, Canada 10/92.
“A Review of Thin Film Technologies in Preparing Thin Film Transistors for Liquid Crystal Displays.”

92.  Department of Chemical Engineering and Materials Science, Columbia University, New York City, 10/06/92.
“Thin Film Transistors and Reactive Ion Etching.”

93.  Department of Radiology, College of Medicine, University of Michigan, Ann Arbor, MI, 05/22/92.
“Self-aligned, Two-photomask Thin Film Transistor - Process and Reliability.”

94.  Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, 09/91.
“Novel Thin Film Transistors and Plasma Etching Processes.”

95.  Electronics Research Organization, Industrial Technology Research Institute,
Hsin-chu, Taiwan, 08/90.
“Plasma Etching in Thin Film Transistor Fabrication.”

96.  Display System Optics Symposium, International Society of Optical Engineers SPIE, 09/89.
“Thin Film Technologies in Active Matrix Addressing Systems of LCDs.”

97.  Xerox Microelectronics Center, ElSegundo, CA, 05/89.
“Plasma Etching of PECVD a-Si:H and SiNx.”

 

Home, TFTs, High k Gate Dielectrics, Low k dielectrics, RIE, PECVD, Biochips, Laboratory, Publications, Activities, Links