The
a-Si:H
TFT is critical to today’s large area, high performance LCDs as well
as for many large area microelectronics. The poly-Si
TFT has been proved to be an effective loading device in SRAM. It has many
potentials in LCD and other high speed (compared with a-Si:H TFT) applications. We study both types of TFTs from different angles. Recently, we invented and
studied a new type of a-Si:H TFT nonvolatile memory, which greatly expands
the application of the low-temperature prepared transistor to new territories.
Plasma enhanced chemical vapor deposition (PECVD) is the
only practical large area, low temperature, high throughput fabrication method
for a-Si:H TFT arrays today.
Although a-Si:H TFTs
function adequately for LCD as well as many new microelectronic and opto-electronic applications, the performance is usually
below the practical limit due to the poor understanding of many process, thin
film materials, and device issues. The a-Si:H/gate SiNx
interface chemical and physical properties are especially critical to the TFT
characteristics. Previously, we have carried out various studies on this
subject. The results can be found in the Publications List.
Currently, we are exploring applications of a-Si:H TFTs to novel electronic
areas.
The following are examples of some topics that we have studied:






Y. Kuo and H. Nominanda, APL 89, 173503 (2006).
H. Nominanda
and Y. Kuo, ECS Trans. 3, (8) 333 (2006).


H. Helinda and Y.
Kuo, ESL 10(8), H232-234 (2007)
Y. Kuo and H. Nominanda,
MRS Proc. 2007.


Y. Kuo, R.
Lei, etc., ECS TFTT VII Symp., 2004.


Y. Kuo, Darpa Macroelectronics Workshop,
11/06/03.

Y. Kuo et al., ECS TFTT VI proc, 2002.


ESCA of Hydrogen Plasma Exposed SiNx
Surfaces


ESCA of Hydrogen Plasma Exposed SiNx
Surfaces
Y. Kuo. Vacuum, 59, 484-491, 1999.
Horizontally redundant, vertically redundant, multi-channel single gate, etc.
Y. Kuo, JECS, 138(2), 637, 1991.
Semiconductor International, Industry News, p. 22, June 1992.

Y. Kuo, JECS, 141(4), 1061, 1994.
Mobilities of Multi-step
Deposited a-Si:H TFTs
Y. Kuo. APL
67(15), 2173. 1995.

Y. Kuo, JECS 142(1), 186, 1995.
Process Induced Damages and TFT Reliability

Y. Kuo, ECS TFTT
IV Symp.,
192, 1998.
The
poly-Si TFT has a much higher mobility than the a-Si:H TFT has. This enables the circuit designers to add
many new functions into the product. However, before the poly-Si TFT is
acceptable for large-area, mass production, its process conditions have to be
compatible with the low temperature substrate. Recently, we published a pulsed
rapid thermal annealing (PRTA) process. When this process is combined with the
metal contact structure, poly-Si can be formed at a high rate, e.g., > 10 micrometers per 1-second pulse, with a low
thermal budget. This method has no limit on the substrate size. This technology
can be used to fabricate not only the large area poly-Si TFT array but also the
shallow junction VLSI devices. Since this is a new technology, there are many
unknown material and process issues. We are examining these fundamental issues
with the goal of fabricating advanced devices. Some of the results are shown
below. For more detailed information, please see the Publications
List.
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Y. Kuo and P. Kozlowski, APL 69(8), 1091, 1996; Y. Kuo, ECS TFTT III,
96-23, 30, 1996.
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