Nonvolatile Memories

Memories are important devices in semiconductor products. Our studies in this area are focused on high-speed nanocrystals embedded high-k memories and the novel low-temperature prepared floating-gate a-Si:H TFT memories. The capacitor is a powerful basic device that can be used to investigate electric properties including dielectric materials, interfaces, structures, and process influences. We built MOS (or MIS) capacitors to screen new doped high-k materials for future MOSFETs. We have also investigated nonvolatile memory functions of the nanocrystals embedded high-k gate dielectrics. We further research on the floating-gate a-Si:H TFT nonvolatile memories. The reliability of the new device, such as the deterioration mechanism and lifetime under accelerated testing conditions, is an integrated part of our research.  

Doped high-k dielectric MOS capacitors (Control Samples)

The doped high-k film’s bulk and interface material, e.g., composition, concentration profile, thickness, bond states, and crystallinity, and electrical properties, e.g., interface density of state Dit, oxide trap density Qot, fixed charge density Qf, and flat band voltage Vfb, with respect to dopant type, concentration, PDA condition, and interface layer composition, have been investigated and reported, see Recent Publication list for details. 

Nanocrystals embedded doped high-k dielectric MOS memories




Q charge trapping density

q electron charge.

DVfb flat band voltage difference between Vfb of forward curve and that of backward curve 





A. Birge and Y. Kuo, J. Electrochem. Soc., 154(10), H887 (2007).


·       nc-Si embedded ZrHfO memory capacitors




J. Lu, Y. Kuo, J. Yan and C.-H. Lin, JJAP 45(34) L 901 (2006).


·        nc-ITO embedded ZrHfO2 - hole-trapping memory capacitors


Y. Kuo, ECS Trans. 3(3), 253 (2006).

Y. Kuo, J. Lu, J. Yan, and C.-H. Lin, IEEE Nano, 2006.


A.  Birge, C.-H. Lin, and Y. Kuo, ECS Trans. 3(3), 193 (2006).



·       nc-ZnO embedded ZrHfOelectron trapping at low bias voltage


C-V curves for control and nc-ZnO embedded capacitors at1MHz.
Cox is the accumulation capacitance measured at -6V.


-         Light illumination provides a large amount of photon-generated electrons in the inversion layer. 

                   Slow electron trapping rate in darkness due to limited supply of free electrons from p-type Si substrate and slow minority carrier generation-recombination rate.

Figure 5. Flatband voltage shift as a function of +6V gate stress time in the dark and under illumination at room temperature.

-         Voltage dependent electron and hole trapping


Figure 6. Flatband voltage shifts as a function of gate stress voltages for a 90s stress time measured in darkness and at room temperature.


-         Excellent electron retention characteristics show that electrons are deeply trapped at the nc-ZnO sites.


Figure 9. Charge retention of nc-ZnO embedded ZrHfO after +6V 90s “write”, -7V, 10s erase, and -8V, 10s “erase” conditions.

J. Lu, C.-H. Lin, and Y. Kuo, ECS Transactions, 11 (4) 509 (2007).

J. Lu, C.-H. Lin, and Y. Kuo, J. Electrochem. Soc. 155(6) H386 (2008).

Selected AIP Virtual J. Nanoscale Sci. and Technology 17(7) (2008).



·       nc-RuO embedded ZrHfO – mainly hole trapping below the ±6V gate bias region


- Holes strongly trapped at nanocrystal site and loosely trapped at its interface 


Fig. Ru 3d XPS spectra of (a) as-deposited and (b) after RTA at 950°C under the 1:1 N2/O2 ambient for 1min.


procedding fig3-2


Top view TEM


Cross-sectional view TEM

Fig. Memory window and flat band voltage of nc-RuOx embedded ZrHfO capacitors.

Fig. J-V curve swept from 0V to –5V then back to 0V. Polarity of current flow: positive (to substrate) or negative (to gate).



Fig. (a) C-V (at 1MHz) curves after stressed at different negative (-5V to –10V) and positive (+5V to +10V) gate voltages and (b) shift of Vfb as a function of the gate stress voltage. The stress time was fixed at 5s.





Fig. G-V curves measured at 1M, 500k, and 100kHz with different gate voltage sweep voltage ranges of (a) control sample and (b) nc-RuO embedded ZrHfO capacitor.



C.-H. Lin and Y. Kuo, ECS Transactions, 13(1) 465  (2008). 

C.-H. Lin and Y. Kuo, ECS Transactions, 16(5), 309 (2008).


·       Dual-layer nanocrystals embedded ZrHfO



(a) ZrHfO control sample.


(d) single-layer nc-ZnO embedded ZrHfO


(e) dual-layer nc-ZnO embedded ZrHfO

C.-H. Lin and Y. Kuo, ESL, 13(3) H83(2010).



Fig. C-V hysteresis curves of control, single-, and dual-layer nc-ZnO embedded samples measured at 1 MHz.

Fig. Shifts of VFB wrt fresh single- and dual-layer nc-ZnO embedded ZrHfO vs. stress time at Vg = +8 V.



Fig. C-V curves of nc-ITO and nc-ZnO embedded capacitors stressed at –8V or +8V for 10ms: (a) single nc-ITO, (b) dual nc-ITO, (c) single nc-ZnO, and (d) dual nc-ZnO embedded in ZrHfO. The measurement was done by sweeping voltage from –2V to 1V.


Fig. Change of Vfb with gate stress time of single and dual (a) nc-ITO and (b) nc-ZnO embedded ZrHfO capacitors. The gate bias voltage was fixed at -8V for nc-ITO and +8V for nc-ZnO embedded samples, respectively.



·       Reliability – relaxation and breakdown mechanisms   

-        higher relaxation currents than the non-embedded high-k film




Fig.  Relaxation current density vs time of nc-ZnO embedded ZrHfO capacitor and control sample.

Fig. Relaxation current normalized to polarization vs time of nc-ZnO embedded ZrHfO and various high-k and SiO2 dielectrics.


Curie-von Schweidler equation


J / P = at n                


J: relaxation current density (A/cm2), P: total polarization or surface charge density (V·nF/ cm2), t:  time in second,

                              a:  a constant, n: a real number 0 < n < 1


C.-H. Yang, Y. Kuo, and C.-H. Lin, Appl. Phys. Letts., 96, 192106 (2010).

-        nanocrystals retain charges in deeply and loosely trapped states


Table. Percentages of deeply and loosely trapped charges for nanocrystal embedded samples after the first 20 seconds.


-        breakdown from the bulk high-k film










nc-ITO & -Si


nc-ITO & -Si


Fig. Ramp-relax test results on nanocrystals embedded high-k films


C.-H. Yang, Y. Kuo, C.-H. Lin, R. Wan, and W. Kuo, MRS Procs. 1071-F02-09 (2008).

C.-H. Yang, Y. Kuo, R. Wan, C.-H. Lin, and W. Kuo, IRPS 46 (2008). 



·       Reliability –breakdowns of single- and dual-layer nanocrystals embedded high-k      



Ramp for Single ITO

Relax for Single ITO



C-V for single ITO

Fig. (a) Jramp-Vg and (b) Jrelax-Vg and (c) C-V curves of a single-layer nc-ITO embedded ZrHfO capacitor measured with the two-step ramp-relax method.

C.-H. Lin and Y. Kuo, ECS Transactions, 19(8), 81 (2009).


C.-H. Lin and Y. Kuo, Electrochem. Solid-State Letts. 13(3) H83 (2009).



·       Reliability –Temperature Influence on Nanocrystals Embedded High-k Nonvolatile CV Characteristics




Fig. CV hysteresis curves for (a) control sample at 25°C, (b) nc-ZnO embedded ZrHfO at 25°C, (c) nc-ZnO embedded ZrHfO at 75°C, and (d) nc-ZnO embedded ZrHfO at 125°C.                           

C.-H. Yang, Y. Kuo, C.-H. Lin, W. Kuo, ESL 14(1), H50 (2011)




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