Thin Film Transistors (TFTs)

The a-Si:H TFT is critical to today’s large area, high performance LCDs as well as for many large area microelectronics. The poly-Si TFT has been proved to be an effective loading device in SRAM. It has many potentials in LCD and other high speed (compared with a-Si:H TFT) applications. We study both types of TFTs from different angles. Recently, we invented and studied a new type of a-Si:H TFT nonvolatile memory, which greatly expands the application of the low-temperature prepared transistor to new territories.

a-Si:H TFTs

Plasma enhanced chemical vapor deposition (PECVD) is the only practical large area, low temperature, high throughput fabrication method for a-Si:H TFT arrays today. Although a-Si:H TFTs function adequately for LCD as well as many new microelectronic and opto-electronic applications, the performance is usually below the practical limit due to the poor understanding of many process, thin film materials, and device issues. The a-Si:H/gate SiN_x interface chemical and physical properties are especially critical to the TFT characteristics. Previously, we have carried out various studies on this subject. The results can be found in the Publications List. Currently, we are exploring applications of a-Si:H TFTs to novel electronic areas.

The following are examples of some topics that we have studied:

Copper Interconnection for TFT
Interface Engineering of TFT
Novel_Structures
Self-aligned, 2-photomask, Tri-Layer TFT Structure and Processes
Graded SiN_x Gate Dielectric TFT
Multi-step a-Si:H Deposition for TFT
Unified Gate SiN_x RI to V_th Relation
Process Induced Damages and Reliability
Pulsed Rapid Thermal Annealing (PRTA)

a-Si:H TFT Nonvolatile Memories

Kuo & Nominanda, APL 89, 173503 (2006). Nominanda & Kuo, ECS Trans. 3, (8) 333 (2006).

Floating-Gate a-Si:H MIS Capacitors

H. Helinda and Y. Kuo, ESL 10(8), H232-234 (2007)

Y. Kuo and H. Nominanda, MRS Proc. 2007.

Bipolar TFT

Y. Kuo, Darpa Macroelectronics Workshop, 11/06/03.

Y. Kuo, R. Lei, etc., ECS TFTT VII Symp., 2004.

P-channel TFT

Y. Kuo, Darpa Macroelectronics Workshop, 11/06/03.

Y. Kuo et al., ECS TFTT VI proc, 2002.

TFT with RIE’d Copper Interconnection

A complete a-Si:H TFT with the source and drain regions composed of Cu and Mo.

ESCA of Hydrogen Plasma Exposed SiN_x Surfaces

Y. Kuo, S. Lee, S. Lee, J. P. Donnelly, J.-Y. Tewg, and H. H. Lee.
ECS TFTT V Symp. Proc. PV 2000-31, 34-39, 2001.

Interface Engineering of TFT

ESCA of Hydrogen Plasma Exposed SiN_x Surfaces

Y. Kuo. Vacuum, 59, 484-491, 1999.

Novel Structures

Horizontally Redundant TFT

- Y. Kuo, J. Electrochem. Soc., 143(8), 2680 (1996).

Non photosensitive, Vertically Redundant 2-Channel a-Si:H TFT
- Y. Kuo, J. Electrochem. Soc., 143(4), 1469 (1996).

Single-Gate, Multi-Channel a-Si:H TFT

- Y. Kuo, Appl. Phys. Lett., 67(21), 3174 (1995).

Unified SiN_x Gate Dielectric RI to V_th Relationship

- Y. Kuo, JES 142(1) 186 (1995)

Critical Power Effect on TFT Characteristics, Materials, and Large-area Processes

- Y. Kuo, APL 63, 144 (1993)

- Y. Kuo, JES 142(1) 186 (1995)

Self-aligned, 2-photomask, Tri-Layer TFT Structure & Processes

Y. Kuo, SPIE 1456 288 (1991)

Y. Kuo, JECS, 138(2), 637, 1991.
Semiconductor International, Industry News, p. 22, June 1992.

Graded SiN_x Gate Dielectric TFT

Y. Kuo, J. Electrochem. Soc., 141(4), 1061 (1994).
This work was selected in “Tech Highlights” of ECS Interface.

Multi-step a-Si:H Deposited TFTs

- Y. Kuo, Appl. Phys. Lett., 67(15), 2173 (1995).

Process Induced Damages and TFT Reliability

Y. Kuo, ECS TFTT IV Proc., 192, 1998.

Poly-Si TFTs

The poly-Si TFT has a much higher mobility than the a-Si:H TFT has. This enables the circuit designers to add many new functions into the product. However, before the poly-Si TFT is acceptable for large-area, mass production, its process conditions have to be compatible with the low temperature substrate. Recently, we published a pulsed rapid thermal annealing (PRTA) process. When this process is combined with the metal contact structure, poly-Si can be formed at a high rate, e.g., > 10 micrometers per 1-second pulse, with a low thermal budget. This method has no limit on the substrate size. This technology can be used to fabricate not only the large area poly-Si TFT array but also the shallow junction VLSI devices. Since this is a new technology, there are many unknown material and process issues. We are examining these fundamental issues with the goal of fabricating advanced devices. Some of the results are shown below. For more detailed information, please see the Publications List.